Academic Research

Zero-Whitespace Rectilinear 3D Floorplanning with Pressure-Driven Orthogonal Laguerre-Voronoi Tessellation (POLT)

System Aware Floorplanning for Chip-Package Co-Design

Chiplet Set for Artificial Intelligence using Advanced Interface Bus (AIB)

Publications

Amin, Fin, Nirjhor Rouf, Tse-Han Pan, Md Kamal Ibn Shafi, and Paul D. Franzon. "Large Reasoning Models for 3D Floorplanning in EDA: Learning from Imperfections." arXiv preprint arXiv:2406.10538 (2024).

T. -H. Pan, P. D. Franzon, V. Srinivas, M. Nagarajan and D. Popovic, "System Aware Floorplanning for Chip-Package Co-design," 2023 IEEE 32nd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Milpitas, CA, USA, 2023, pp. 1-3, doi: 10.1109/EPEPS58208.2023.10314897.

J. A. Stevens, T. -H. Pan, P. P. Ravichandiran and P. D. Franzon, "Chiplet Set For Artificial Intelligence," 2023 IEEE International 3D Systems Integration Conference (3DIC), Cork, Ireland, 2023, pp. 1-5, doi: 10.1109/3DIC57175.2023.10154953.

T. Nigussie, T. -H. Pan, S. Lipa, W. S. Pitts, J. DeLaCruz and P. Franzon, "Design Benefits of Hybrid Bonding for 3D Integration," 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2021, pp. 1876-1881, doi: 10.1109/ECTC32696.2021.00296.